Present-day computers are requiring more and more memory. This is partly because improvements in CPU performance have outpaced the speed improvements of hard disk drives in the past decade. To improve system performance while minimizing the access to the relatively slow hard drive, large amounts of memory are being added to the computer systems to hold computer programs and data. Also, in addition to more memory, higher-speed memory is increasingly important to ensure that memory bandwidth requirements for ever-increasing CPU speeds can be met.
Memory for computers, such as dynamic random access memory (DRAM), is normally mounted together on a printed circuit board (PCB) to form a memory module. Memory modules come in different sizes and shapes, also referred to as the “form factor.” The form factor dictates the number of memory chips that can be assembled on a module, as well as the pin configuration of the module. Examples of memory module configurations include 30- and 72-pin single in-line memory modules (SIMMs), and 168-pin and 184-pin dual in-line memory modules (DIMMs). DIMMs closely resemble SIMMs, with the principal difference being that on a SIMM, pins on opposite sides of the printed circuit board are tied together to form one electrical contact. On a DIMM, in contrast, opposing pins remain electrically isolated to form two separate contacts.
Because they have more contact pins, DIMMs are more popular than SIMMs. DIMMs include such variants as the small-outline DIMM (SO-DIMM) and micro DIMM, which are smaller in PCB area than a regular DIMM and have different pin configurations.
A memory module allows a set of memory chips to be accessed simultaneously (i.e., in parallel) and allows more data bits to be read or written at a time to increase the memory bus bandwidth. For example, a typical 256 MB double data rate (DDR) DIMM contains eight or nine 32 M×8 bit synchronous DRAM chips, utilizes a 184-pin connector, and is capable of transferring 64 or 72 bits of data at a time with a 167 MHz memory bus clock, to achieve a bandwidth of 2700 Megabytes per second. As the number of memory chips in a module increases, the capacitance loading of the memory module on the memory bus also increases, slowing down the memory access.
There are two basic types of memory chips in general—asynchronous and synchronous. Like its name suggests, an asynchronous memory chip does not operate based on any kind of common system clock. The memory controller must manipulate the timings of the data, address, and control signals of asynchronous memory chips to access them. Examples of types of asynchronous memory chips include Fast Page Mode (FPM) DRAM, Extended Data Out (EDO) DRAM, and Flash memory.
In contrast, synchronous memory, like synchronous DRAM (SDRAM), shares the same system clock with the memory controller. This simplifies the timing considerations for memory accesses. All memory transfers are simply referred to the rising and falling edges of the clock. Synchronous memory can also take advantage of the pipelining features enabled by the use of a clock to control memory operations, which make memory retrieval even faster. Synchronous memory modules come in several different speeds synchronized to the system clock they will be used in. For examples, a PC100 SDRAM module runs at 100 MHz on the front-end bus clock in a personal computer, and a PC133 SDRAM module runs at 133 MHz, etc. A double data rate (DDR) SDRAM module, which allows data to be transferred on both the rising and falling edges of the clock cycle, yields an effective data rate of 266 MHz or 333 MHz, at 133 MHz or 167 MHz clocks, respectively.
There are three basic “types” of memory modules: unbuffered, buffered, and registered. These designations refer to how the memory modules process the control and address signals (herein collectively referred to as the “control signals”) received over a memory bus from a memory controller.
An unbuffered module is the most common memory module. The memory chips in an unbuffered module can be synchronous or asynchronous. Unbuffered modules are assembled with a set of memory chips on a printed circuit board, but do not have means to re-drive the control singles received from the memory controller. The memory controller must drive the complete set of memory chips on an unbuffered module, which in some cases can be as high as 36 chips per module. When a memory module with 36 chips is inserted into a socket, the memory controller will encounter a 36-times load increase for every address line and control signal it controls. For this reason, a PC motherboard designed to use unbuffered memory modules only supports a very limited number of unbuffered modules—normally, two to four modules.
An example of an unbuffered module 100 is shown in FIG. 1. As shown, the unbuffered module contains a set of memory chips 102-1 . . . 102-n, which are directly connected to the edge connector 112 of the PCB (these connections are not explicitly shown). The edge connector 112 contains a set of contact pads, where data bus 140, address and control bus 120, and power and ground 190 are in electrical connection with the module. The unbuffered module may also contain a number of passive components (not shown), such as serial damping resistors for single-ended signals, termination resistors for differential signals, compensation capacitors to balance loading, and decoupling capacitors between power and ground to reduce noise. The module may also contain a set of pull-up/pull-down resistors or a serial EEPROM chip 130 at serial presence detect (SPD) interface 131 that can be queried by the memory controller to obtain module configuration and timing information.
Because the memory chips 102-1 . . . 102-n are directly connected to the contact pads of the edge connector 112, the address/control signals from the memory controller have to drive all of the memory chips. (Only one representative control signal is shown in the figure). Additionally, if the memory chips 102-1 . . . 102-n are synchronous, the system clock signal 230 received by the module (e.g., from the front-end bus clock of a motherboard) provides the timing signal for all of the memory chips on the module.
Without buffers, registers, or other supporting chips, an unbuffered module is the most cost-effective module and is normally used in desktop PCs, where cost is a major concern. However, unbuffered modules may not be able to meet the requirement of future high-speed and high-capacity memory systems because the heavy load on the control signals can slow down the memory bus. Buffered modules and registered modules, while reducing memory bus loading, are more expensive, and are normally reserved for use in servers and other high-end systems.
Buffered modules are used in asynchronous DRAM applications, such as EDO memory modules. A buffered memory module utilizes driver integrated circuits (ICs) or buffers to improve module performance by “re-driving” the control signals in the memory module. Adding buffers to a memory module electrically isolates the memory chips on the module from the memory bus, effectively reducing the loads seen by the memory controller. The buffers also help the memory controller cope with the capacitance load caused by the memory chips on the module. Using a buffered EDO memory module as an example, system performance is improved by having the input control and address signals buffered (except for the RAS# signal and data). The Samsung M372F3200DJ3-C 32 Mx72 EDO DIMM module, for example, uses thirty-six 16 M×4 bits DRAMs and contains two 16-bit driver ICs. Leaving the data and RAS# signals unbuffered preserves the DRAM timing specifications for the module.
Another type of buffering seen in asynchronous DRAM modules is the adding of bus switch ICs to the data bus of the memory module. The bus switch isolates the data signals from the memory bus under system control. Only the data signals of a selected (enabled) memory module are connected to the system data bus, while the data signals of all unselected memory modules are disconnected (e.g., tri-stated) from the data bus by disabling the bus switch buffers. Since an asynchronous memory module does not require a clock signal, there is no Phase Lock Loop (PLL) or similar clock buffer, such as a Delay Locked Loop (DLL), in such a memory module. In some cases, driver ICs and Programmable Logic Devices (PLD) are also added to asynchronous memory modules. For example, the Dataram DRS1500/512 Mezzanine Memory Board, organized as four banks of 8 M×144 bits, consists of seventy-two 8 M×8 bits EDO DRAMs, five 16-bit buffer/drivers, and one programmable logic device (PLD). The PLD controls the WRITE Enable and Output Enable signals to the DRAM chips.
In synchronous memory modules, the system clock controls the timing of data transfers in the memory. The clock is input to every synchronous memory chip on the module. To reduce the loading to the system clock due to the insertion of a memory module, and to control the clock skew among memory chips with respect to the system clock, a PLL or DLL can be added to this type of memory module to synchronize the clock signals among the memory chips. A PLL or DLL takes the system clock input as a reference clock, and regenerates it into multiple outputs with either no delay or a controlled delay, before distributing the clocks to the memory chips on the memory module.
Generally, unregistered driver ICs have not been utilized to reduce the loads of control signals in a synchronous memory module where a PLL or a clock buffer is used. Normally, only register chips or registered buffers are used to buffer the control signals in a synchronous memory module. A synchronous memory module with a PLL and register buffers to register the control signals is referred to as a “registered” memory module.
An example of a registered memory module 200 is shown in FIG. 2. The components in a registered memory module include a set of synchronous memory chips 202-1 . . . 202-n, an edge connector 112, passive components (not shown), and a Serial Presence Detect (SPD) EEPROM 130. The edge connector 112 contains a set of contact pads (not shown) for electrically connecting data bus 140, system clock bus 230, address and control bus 120, and power and ground 190 to the module. The edge connector 112 also includes an SPD interface 231. The registered memory module 200 contains more active components than the unbuffered memory module shown in FIG. 1—e.g., register 210 and phase locked loop (PLL) 212. For the registered memory module 200, the address and control signals (from bus 120) drive the register 210, which registers the address and control signals from the memory bus. The register 210 then drives the address and control signals to the synchronous memory chips 202-1 . . . 202-n. PLL 212 receives the system clock (i.e., the reference clock, from system clock bus 230), buffers it, and then distributes it to the register 210 and to all of the synchronous memory chips 202-1 . . . 202-n. PLL 212 acts as a clock buffer, and is also used to minimize the clock skew among the memory devices.
Registered modules are particularly advantageous in servers and high-end workstations where greater amounts of memory are needed, and where the timing requirements are more stringent. A system using registered memory modules can support more memory modules. For example, some motherboards using registered memory modules can have 8 or even 16 memory modules installed on it at one time. This is because every control signal from the memory controller only sees one load for every registered memory module installed in the computing system. This is very different from an unbuffered memory module, where every control signal from the memory controller has to drive all of the memory chips on the memory module. With a lighter load on the memory bus, a shorter cycle time and higher operating frequency is possible for the registered memory modules.
The register chips or the registered buffers in a registered memory module introduce a new pipeline stage to the control signals in the memory access and cause the control signals input to the registered memory module to encounter a delay cycle latency. The delay cycle in the control signals causes a registered memory module to function differently than an unbuffered memory module. As a result, the memory module manufacturers are required to maintain two sets of synchronous memory modules—one for registered applications and one for unbuffered applications.
Each type of memory module—unbuffered, buffered, and registered—has different advantages and disadvantages. Yet, significantly, a memory module of one type cannot be used interchangeably in a system designed to use another type. In other words, systems that are designed to use registered memory modules will not function correctly if unbuffered memory modules are inserted, and vice-versa, principally due to the consideration of an extra delay cycle of the registered memory modules. There are different keying notches on the memory modules and on the system memory sockets to help ensure that only the correct type of memory modules are installed into the system.